1. Field of the Invention
The invention relates to methods and circuits for phase matching of a periodic input signal, with reduced sensitivity to disturbances during an initial transient phase.
2. Description of the Related Art
DLL circuits (delay locked loops) are used in order to produce signals which are intended to have a fixed phase difference with respect to a given periodic input signal. DLL circuits such as these are frequently used in clock signal lines in integrated circuits, in order to compensate for the propagation time delay on the clock signal line. In the case of a delayed clock signal, the DLL circuit then adds a further delay to the clock signal, so that a phase-matched signal is produced at the output of the DLL circuit, with this phase-matched signal being delayed by one clock period or by a multiple of a clock period with respect to the original undelayed clock signal. In this way, it is possible to provide an undelayed clock signal at the output if, for example, the signal propagation time on the signal path of the clock signal is known at every point in the integrated circuit as far as the DLL circuit.
The accuracy of the phase matching depends on how accurately the previous delay of the clock signal can be modeled with the aid of a replication in the form of a delay element.
A DLL circuit typically has a variable delay unit, which is set via a regulation unit. The regulation unit also has a comparator unit, which compares the periodic signal and the input signal which has been delayed via the variable delay unit and the delay element with one another, and generates a phase signal which indicates whether the input signal is leading or lagging. In the steady state, the phase signal indicates whether the delay of the variable delay unit should be incrementally increased or reduced.
In an initial transient phase, for example shortly after the DLL circuit has been switched on, a steady state must first of all be found, in which the input signal and the signal which has been delayed by the delay unit and the delay element essentially have a phase angle of 0°, or are oscillating around a phase angle of 0°. As the initial state, a specific delay is set in the variable delay unit, in which case, if a lead is identified, this does not indicate whether the phase angle of 0° can be achieved reliably by reducing the delay in the delay unit. For this reason, the delay in the variable delay unit is increased continuously in the initial transient phase, independently of the phase signal, with greater increments than in the steady state. If it is found, after having previously identified that the input signal is leading, that the input signal is now lagging, then the phase angle of 180° has been reached. If a lead is detected after a lag, then the phase angle of 0° has been reached, the initial transient phase is ended, and a change is made to the normal operating state.
When the phase signal changes at a phase angle of 180°, it is possible in the event of disturbances for a lead to be identified once again after a change has been identified from a lead to a lag, so that the regulation unit incorrectly assumes that the phase angle of 0° has already been reached. This leads to a change in the regulation to the normal operating mode, in which the delay in the delay unit is changed with considerably smaller increments than in the initial transient phase, so that it takes a very long time to set the phase angle to 0°. As a result, it may not be possible to reach a maximum initial transient time that is stipulated according to a specification.